1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device such as static type random access memory circuit device.
2. Description of the Prior Art
As stated in 1987 ISSCC (IEEE International Solid-State Circuits Conference) Digest of Technical Papers, pp. 260-261, and 1985 ISSCC Digest of Technical Papers, pp. 58-59, a memory circuit device in the prior art recovers a potential level chop of a bit line after the writing of memory cell information, in such a way in which an n-channel MOS transistor which is the load of the bit line (or a data line) is controlled into its conductive or non-conductive state by a WE signal which is the inverted signal of a write enable signal or a pulse signal which is produced from the WE signal.
In another memory circuit device in the prior art, as illustrated in FIG. 4, transfer gate MOS transistors Q.sub.50 -Q.sub.52 are brought into their conductive states by a signal .phi..sub.L, thereby to transmit sense amplifier complementary output data D, D to a latch circuit 10 and an output buffer 20.